DE 690 30 772 T2 describes a divider for performing a fast arithmetic operation. The divider is used for generating a quotient by dividing a dividend by a divisor. A first latching device contains the dividend data characterizing the dividend. A second latching device contains the divisor data characterizing the divisor. An operational device generates either a sum or a difference between the dividend data and the divisor data. In the divider, a third latching device is also provided which is used for latching sign bit data. An inverting device is provided for inverting the sign bit data. The divider also contains a shifting device for sequentially shifting the inverted sign bit data from a least significant bit position when the inverted sign bit data from the inverting device are input whilst the inverted sign bit data are latched. A further shifting device is provided for arithmetically shifting the result data, generated by the operational device, by one bit to the left whilst a logical ZERO is stored in an LSB position. A control device is used for controlling the execution of the iterative division processing by controlling the operational device and the two shifting devices so that the operational device generates a sum or difference on the basis of the temporarily stored sign bit data. The second shifting device doubles the operation result generated by the operational device, the first latching device temporarily storing the doubled result.
DE 695 04 192 T2 describes a circuit arrangement for digitally performing a division operation according to the method of disregarding the intermediate remainder.
In many applications, it is necessary to divide a fixed-point signal, which consists of a sequence of n-bit-wide digital data values, by a fixed dividing factor.
FIG. 1 shows a calculating circuit for dividing an applied fixed-point input signal by an adjustable dividing factor for generating a divided fixed-point output signal according to the prior art. The conventional fixed-point dividing circuit shown in FIG. 1 has a signal input E for applying the fixed-point input signal to be divided. The fixed-point input signal consists of a sequence of n-bit-wide digital data values which are applied to the signal input E of the fixed-point dividing circuit via n data lines.
The sequence of n-bit-wide digital data values passes via internal data lines of the fixed-point dividing circuit to an addition circuit ADD which adds the applied digital data value of the fixed-point input signal to a data value temporarily stored in a register R. The register R is connected to the addition circuit ADD via k data lines for delivering a k-bit-wide temporarily stored digital data value. The addition circuit ADD adds the applied digital data value of the fixed-point input signal to the k-bit-wide data value temporarily stored in the register R to form an aggregate data value which has max(n,k)+1 data bits. The aggregate data value is delivered to a signal input of a splitting circuit SPLIT via data lines.
The splitting circuit splits the max(n.k)+1-bit-wide applied aggregate data value into a first data value which consists of a least significant data bits of the aggregate data value, and into a second data value which consists of the most significant data bits of the aggregate data value. The first data value is delivered via max(n,k)−k+1 data lines to a signal output A of the fixed-point dividing circuit. The noise added by the fixed-point dividing circuit can be filtered out by a subsequent digital filter. The second data value is temporarily stored in the register R via a data lines and fed back to the addition circuit ADD.
In the text which follows, the operation of the fixed-point dividing circuit according to the prior art as shown in FIG. 1 is explained by means of an example. In this example, the fixed-point dividing circuit divides the applied fixed-point input signal by a dividing factor of 4, the number of fed-back, least significant data bits of the second data value a delivered by the splitting circuit being=2. If a constant signal sequence of 4-bit-wide digital data values with a constant value of 3 (3=0011) is applied to the signal input E of the fixed-point dividing circuit, the fixed-point dividing circuit of the prior art as shown in FIG. 1 produces the following sequence of data values:
TABLE 1E3333 3333 . . .R0321 0321 . . . A0111 0111 . . . 
From the output data sequence A, the mean value of the output signal, which is 0.75 in the example shown, is calculated in a subsequent calculating circuit. The constant input signal having the value 3 is divided by the dividing factor 4 by the fixed-point dividing circuit to become the value ¾=0.75.
However, the conventional fixed-point dividing circuit of the prior art shown in FIG. 1 has the disadvantage that, in the case of an alternating input signal, the variance of the fixed-point output signal delivered by the fixed-point dividing circuit rises. If, for example, an alternating signal sequence with alternating digital data values +3, −3 is applied to the signal input E of the fixed-point dividing circuit of the prior art, the following data sequence is obtained. The negative data values are represented in binary form as two's complement, i.e. the positive data value +3 corresponds to the binary value 0011, and the negative data value −3 corresponds to the binary coded data value 1101.
TABLE 2E+3−3+3−3+3−3+3−3R01010101A+1−1+1−1+1−1+1−1
As can be seen, the conventional fixed-point dividing circuit delivers an output signal which fluctuates between the digital value +1 and −1 when an alternating input signal is present. Thus, the variance of the output signal is not zero.
When such a conventional fixed-point dividing circuit is used in a feedback-type control loop, the value delivered by the fixed-point dividing circuit will fluctuate and thus reduce the stability of the control.
For this reason, the calculating circuit represented in FIG. 2 was proposed. The calculating circuit represented in FIG. 2 was filed as a German patent application with the patent application number 100 55 659.0. The calculating circuit shown in FIG. 2 is used for dividing a fixed-point input signal which consists of a sequence of n-bit-wide digital data values and which is present at the signal input F. The fixed-point input signal is divided by an adjustable dividing factor 2k for generating a divided fixed-point output signal. The calculating circuit exhibits a signal input F for applying a data value sequence of the fixed-point input signal. The calculating circuit also contains a first addition circuit ADD which adds the digital data value present at the signal input E to a data value temporarily stored in a register R to form a max(n,k+1)+1-bit-wide first aggregate digital data value. A shift circuit SPLIT shifts the applied first aggregate data value formed to the right by a data bits so that the max(n,k+1)−k+1 higher-order data bits of the first aggregate data value are delivered to an output of the shift circuit SPLIT. The calculating circuit according to the prior art as shown in FIG. 2 also contains a logic circuit which logically ANDs the k lower-order data bits of the first aggregate data value to a logical data value or logically ORs these bits with the inverted logical data value in dependence on the sign of the first aggregate data value and delivers them to the register R for temporarily storing the logically combined data value Dv1, Dv2.
The calculating circuit of FIG. 2 also contains a second addition circuit ADD which adds the data value delivered by the shift circuit SPLIT to a stored value of one for eliminating the DC component in dependence on the sign of the first aggregate data value to form a second aggregate data value. A sequence of the second aggregate data values is delivered as a divided fixed-point output signal at a signal output A.
The two multiplexers MUX of the calculating circuit as shown in FIG. 2 are driven by a sign detection circuit. The sign detection circuit is used for detecting the sign of the first aggregate data value. When a positive sign of the first aggregate data value is detected by the sign detection circuit, the multiplexer of the second addition circuit ADD switches the data value delivered by the shift circuit SPLIT through to the signal output A of the calculating circuit. When a negative sign of the first aggregate data value is detected, the multiplexer of the second addition circuit ADD switches the second aggregate data value delivered by the adder through to the signal output A of the calculating circuit.
If the sign detection circuit detects a positive sign of the first aggregate data value, the first logically combined data value DV1 is switched through to the register R by the multiplexer and, when a negative sign of the first aggregate data value is detected by the sign detection circuit, the second logically combined data value DV2 is switched through to the register R by the multiplexer MUX. The logic A of the logic circuit shown in FIG. 2 is a logical AND circuit which logically ANDs the k lower-order data bits of the first aggregate data value formed with a logical data value. The logic B contained in the logic circuit is a logical OR circuit which logically ORs the k lower-order data bits of the first aggregate data value formed with the inverted logical data value. The logical data value is equal to the dividing factor which is reduced by the value 1. The dividing factor is a power value with the base two and the exponentiation factor k, the exponentiation factor k corresponding to the number of data bits which are shifted to the right by the shift circuit SPLIT.
The known calculating circuit shown in FIG. 2 supplies a divided fixed-point output signal which exhibits low variance with a fixed-point input signal sequence which also contains negative digital data values, as shown by the following example:
If a fixed-point input signal sequence of digital data values which alternate between +3 and −3 is applied to the signal input E of the calculating circuit, the data sequences specified below are obtained in the register R and at the output A of the calculating circuit:
TABLE 3         E−3+3−3+3−3+3−3R0−30−30−30A0000000
As can be seen by comparing the two tables 2, 3, both the fixed-point dividing circuit of the prior art as shown in FIG. 1 and the known calculating circuit as shown in FIG. 2 supply an output signal having the mean value 0. In the fixed-point dividing circuit according to FIG. 1, however, the output signal fluctuates between the value +1 and −1 whereas the output settles to a fixed value in the known calculating circuit according to FIG. 2.
The disadvantage of the known calculating circuit shown in FIG. 2 consists in that the output signal A is not completely free of DC components since the quantization characteristic is not completely symmetric.
In the known calculating circuit of the prior art as described in the patent application Ser. No. 100 55 659.0, the following output signal is obtained with a digital input signal in which the input values, for example, alternate between +5 and −5:
TABLE 4         E−5+5−5+5−5+5R0−10−10−1A−11−11−11
If the same input signal sequence is selected, but with a different starting value, the following table is obtained:
TABLE 5E+5−5+5−5+5−5R01−41−41A100000
As can be seen by comparing Table 4 and Table 5, the output signal A is still free of mean or DC components after the settling process, but the two output signals A have a different variance depending on the starting value of the data sequence.